As noted in “The evolution of IBM CMOS DRAM technology”, E. Adler et al., IBM Journal of Research and Development, Volume 39, Number 12, 1995, the one-device DRAM cell, invented at IBM by R. Dennard, consists of a cell transistor with the drain (or source) connected to one node of the cell storage capacitor, the source (or drain) connected to a bit line, and the gate connected to the word line, which runs orthogonal to the bit line. The requirement to have a large capacitor in a small space with low leakage is the main driver of DRAM technology. A brief description of the cell operation will help to explain why. To write, the bit line is driven to a high or low logic level with the cell transistor turned on, and then the cell transistor is shut off, leaving the capacitor charged high or low. Since charge leaks off the capacitor, a maximum refresh interval is specified. To read, or refresh the data in the cell, the bit line is left floating when the cell transistor is turned on, and the small change in bit-line potential is sensed and amplified to a full logic level. The ratio of cell capacitance to bit-line capacitance, called the transfer ratio, which ranges from about 0.1 to 0.2, determines the magnitude of the change in bit-line potential. A large cell capacitance is needed to deliver an adequate signal to the sense amplifier. As further noted in this article, in a folded bit-line configuration, a cell is crossed by two word lines and one bit line. One of the word lines (WL1) is the “active word line” for the cell, and forms the gate of the cell device. The second word line (WL2), the “passing word line,” is the gate of the cell device on the adjacent cell.
FIG. 1 illustrates two (an adjacent pair of) DRAM cells 100, 100′ of the prior art, and FIG. 1A illustrates an equivalent circuit for a single DRAM cell 100. The DRAM cells are fabricated in a silicon wafer 102 which may be lightly doped. For each DRAM cell, a deep trench 104 is formed in the wafer, extending from the top surface of the wafer into the wafer. A typical trench for a DRAM cell would have depth (vertical on the page) of approximately 60,000 Angstroms (6000 nm, 6 μm), a width (across the page) of approximately greater than 1000 Angstroms (>100 nm, >0.1 μm), and a length (into the page) of approximately greater than 2000 Angstroms (>200 nm, >0.24 μm), two side walls (shown) and two end walls (not shown). Two trenches are shown in FIG. 1. The elements in the trench on the left are numbered (###), and the elements in the trench on the right are labeled (text). In a DRAM device, there would be a great multitude of such trenches and DRAM cells. Each DRAM cell 100 comprises a cell capacitor 110 and a transfer device 120. Word lines and bit lines are omitted from the view of FIG. 1, for illustrative clarity. In the main hereinafter, the construction of a single DRAM cell is described.
The cell capacitor 110 is formed at a bottom portion of the trench and comprises a first plate 112, a second plate 114, and a dielectric (node dielectric) 116 separating the two plates. The first plate 112 is simply a heavily doped region in the wafer adjacent a bottom portion of the trench. The second plate 114 (sometimes referred to as “node plate”) is a conductive structure which is formed in the bottom of the trench; in this example, n+ (arsenic doped) polysilicon. The node dielectric 116 is suitably nitride or oxynitride formed in the bottom portion of the trench. The height of the cell capacitor 110 is typically approximately 3-6 μm, and it typically has a capacitance of approximately 20-40 fF.
The transfer device 120 which is a field effect transistor (FET) is formed at a top (upper) portion of the trench (above the cell capacitor 110) and comprises a source region 122 disposed adjacent the trench, a drain 124 disposed adjacent the trench and vertically spaced from the source 122, and a gate 126 disposed in a top portion of the trench adjacent to and in proximity with both of the source and drain. The source region 122 is diffusion into the wafer from a buried strap (BS) 128. Trench Top Oxide (TTO) 132 is disposed atop the strap 128, between the strap 128 and the gate 126. It isolates (insulates) the gate 126 from the capacitor 110 in the bottom (lower) portion of the trench. Channel oxide 134 is disposed between the sides of the gate 126 and the trench sidewalls. The substrate above the lower edge of collar is doped to form a p-well 150.
The strap 128 is connected to the plate 114 of the cell capacitor by a storage node conductor (or simply, “node”) 136 which is surrounded by a collar 138 of oxide. (The storage node conductor 136 connects the cell capacitor 110 to the cell transistor 120.) The storage node conductor 136 comprises n+ polysilicon, has a length of >1 μm and has a thickness of >40 nm. The collar 138 comprises oxide, has a length of >1 μm (same as the node conductor 136) and has a thickness of >30 nm.
In the equivalent circuit of FIG. 1A, the source (S) can be swapped for the drain (D), depending on the chosen polarity of the overall circuit. One of the source or drain is connected to the node plate of the cell capacitor, the other of the source or drain is connected to the bit line (not shown). The gate (G) of the cell transistor is connected to the word line (not shown).
The processes for forming the DRAM cells 100, 100′ described hereinabove are contemporary DRAM process steps. The following US Patents are cited as being exemplary of various techniques, processes and materials which may be used to implement the present invention. They are intended to provide a general background relating to various contemporary DRAM process steps, not an exhaustive education on the subject.
U.S. Pat. No 6,184,549, issued Feb. 6, 2001 to Furukawa et al. (IBM), discloses trench storage dynamic random access memory (DRAM) cell with vertical transfer device. As discussed therein, as DRAM cells are scaled to meet chip-size requirements for future generations, the channel length of transfer devices on the surface of the silicon substrate can no longer be scaled without degrading off-state leakage requirements (or retention time requirements). Process steps become complex and incompatible with standard DRAM processes, when vertical transfer devices in the DRAM cell are employed to decouple the channel length from layout ground rules.
U.S. Pat. 6,414,347, issued on Jul. 2, 2002 to Divakaruni et al. (IBM), discloses a vertical MOSFET. As discussed therein, trench capacitors are frequently used with DRAM cells. A trench capacitor is a three-dimensional structure formed into a silicon substrate. This is normally formed by etching trenches of various dimensions into the silicon substrate. Trenches commonly have N+ doped polysilicon as one plate of the capacitor (a storage node). The other plate of the capacitor is formed usually by diffusing N+ dopants out from a dopant source into a portion of the substrate surrounding the lower part of the trench. Between these two plates, a dielectric layer is placed which thereby forms the capacitor.
U.S. Pat. No. 6,583,462, issued Jun. 24, 2003 to Furukawa et al. (IBM), discloses vertical DRAM having metallic node conductor. A dynamic random access memory (DRAM) device is formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a metallic storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. Preferably, the trench has an aspect ratio of greater than 50. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness. A signal transfer device includes a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap, a gate insulator having a gate insulator thickness formed on the trench side wall above the first buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator. The signal transfer device of the memory device (200) includes a first diffusion region (214), coupled to the storage node conductor (208) by a buried strap (216), and a second diffusion region (218). The channel region (228) is controlled by the gate conductor (220) and a gate dielectric (222). The gate conductor (220) is coupled to the word line (224). The gate conductor (220) is isolated from the channel region (228) by the gate oxide layer (222) which is either grown thermally or deposited. The second diffusion region (218) is coupled to the bit line contact (227) and a bit line (226).
The ongoing development of DRAMs is in the direction making the memory cells smaller and smaller, so that more memory cells can fit in a given small area (e.g., on a chip). For example, cell size was reduced by a factor of 18.8 in the time between the 4 Mb and 256 Mb generations.
The following articles discuss some of the challenges facing development of sub-100 nm generation DRAM cells:—“Challenges and future directions for the scaling of DRAM,” J. Mandelman et al., IBM Journal of Research and Development, Volume 46, Number 2/3, March/May 2002, page 187-212.—“A highly manufacturable 110 nm DRAM technology with 8F2 vertical transistor cell for 1 Gb and beyond,” H. Akatsu et al., 2002 IEEE Symposium on VLSI Technology, page 52-53—“A highly cost efficient 8F2 DRAM cell with a double gate vertical transistor device for 100 nm and beyond,” R. Weis, 2001 International Electron Device Meeting (IEDM), page 415-418
The scaling down of traditional trench DRAM to sub-100 nm generations is limited, among other things, by issues related to the buried strap (BS) and the traditional collar scheme.
With regard to the buried strap, increased leakage current or even shorts (“short circuits”) could occur due to the interaction of neighboring buried straps caused by the reduced space in sub-100 nm generations. (See, for example, the buried straps 128 of FIG. 1.) In addition, device performance is degraded due to the undesired buried strap to p-well junction capacitance.
With regard to the traditional collar scheme, a minimum collar thickness of 30 nm is required in order to suppress the parasitic leakage between the buried strap (e.g., 128, FIG. 1) and the buried plate (e.g., 114, FIG. 1). For traditional trench DRAM, the collar is deposited inside the trench (within the opening of the trench). As the trench size shrinks beyond 100 nm, the trench opening becomes less than 40 nm (100 nm-(2×30 nm)) after collar deposition. Filling such narrow trenches with poly becomes extremely difficult, and the consequent poly seams (voids) dramatically increase the resistance, which consequently severely degrades the device performance. Additionally, the minimum collar length of 1 μm (1000 nm) is also required to suppress the parasitic leakage path. For sub-100 nm generations, maintaining the minimum of trench capacitance of 40 fF/cell becomes increasingly challenging as both trench size and trench depth are reduced. Unfortunately, trench capacitance cannot be increased by reducing the collar length in the traditional inside collar scheme due to the minimum length requirement to suppress parasitic leakage.
In view of the foregoing, it would be desirable to provide an improved technique for DRAM cell construction which is suitable for sub-100 nm trenches, using techniques which are compatible with contemporary DRAM process steps.